Leadless packaged semiconductor devices are known to provide advantages over leaded packages. Those advantages include better electrical performance in terms of reduced lead inductance, good heat dissipation by use of an exposed thermal pad to improve heat transfer to a PCB (printed circuit board), reduced package thickness and smaller footprint, which reduces the area occupied on a PCB. Examples of leadless packaged semiconductor devices include QFN (quad-flat no-lead devices) and DFN (discrete-flat no-lead devices). However, a disadvantage of leadless packaged semiconductor devices is that inspection of solder joints when mounted on a PCB can be difficult. Conventional inspection techniques utilise so-called Automated Optical Inspection (AOI) systems, whereby a camera scans the leadless packaged semiconductor devices mounted on the PCB for a variety of defects such as open circuit connections, short circuit connections, thinning of the solder connections and incorrectly placed devices. Due to the semiconductor device I/O terminals being arranged on the bottom of the device, and therefore hidden from view when the device is mounted a PCB, it is not generally possible to use AOI systems with leadless semiconductor devices. Automatic XRay Inspection (AXI) systems may allow inspection of solder joints, however AXI systems are expensive.
A solution allowing solder joints to be inspected by AOI is to include a metal side pads which extend from the device I/O terminals on the bottom of the device at least partially up external sidewall of the device. Typically the metal side pads may be formed of tin, lead or tin-lead alloys. During soldering processes attaching the device to the PCB, the solder will wet the I/O terminal on the bottom of the device and also the metal side pads. As a result a portion of the solder joint will be visible allowing inspection by AOI techniques. The solder joint may be considered good, provided that the metal side pads are correctly soldered even if the I/O terminal is not correctly soldered to the PCB.
In addition to ease of inspection, metal side pads may reduce tilting of the device when mounted on a PCB. Metal side pads may also improve shearing and bending performance because of the increased soldered area.
Typically, a package structure will comprise an array of device dies embedded in an encapsulation layer. The device dies will be connected to a leadframe by any appropriate means, such as eutectic bonds. The process of forming a such leadless device involves dividing a two dimensional array of encapsulated integrated circuits into individual semiconductor device packages using a series of parallel row cuts and parallel column cuts. The first series of parallel cuts extend fully through the leadframe and encapsulation layer defining rows of the array.
After electro-plating metal side pads, a second series of parallel cuts is made extending fully through the leadframe and encapsulation layer. This separates the columns of the array thereby providing singulated packages. In such a process the I/O terminals will be exposed and since the I/O terminals are mutually electrically connected the exposed I/O terminals may be electroplated to form the metal side pads. The electrical connection is necessary to maintain electrical continuity so that the electroplating process can be achieved.
However, for leadless semiconductor devices having two separate functional dies and at least three I/O terminals located at one sidewall of the device and at least two I/O terminals located at an opposing sidewall, it may not be possible to form side pads by electroplating according to above process because the cutting sequence requires that middle I/O terminals located at one sidewall of the device formed on a leadframe structure on lead frame will be electrically isolated. FIG. 1a shows a typical lead frame structure 10 formed of a series of lead frame sub-structures.
Prior to the first cutting sequence to define rows, as discussed above, each of the six I/O terminals 12, 14 and 16 (three I/O terminals on two opposing sides of the device) for a specific device lead frame are electrically interconnected connected since they will be monolithically formed from a single piece of metal, typically by a photo etching process on sheet metal. Referring now to FIG. 1b, following the first cutting sequence (indicated by lines A) I/O terminals 12, 14 will be detached from the leadframe structure 10, and therefore it will not be possible to electroplate the I/O terminals 12, 14 to form metal side pads because they will be mechanically detached and electrically isolated from the leadframe structure.
Following the second cutting sequence which is substantially orthogonal to the first cutting sequence, (indicated by lines B) each individual sub-lead frame will be singulated from the leadframe structure 10.